1. Field of the Invention
The present invention relates to a method for manufacturing an insulated gate field effect transistor.
2. Description of the Related Art
Currently, miniaturization of transistors is being advanced based on the so-called scaling rule, and thereby enhancement in the integration degree and the operating speed of semiconductor devices is being promoted. For miniaturization of an insulated gate field effect transistor (metal insulator semiconductor FET (MISFET)), it is demanded to suppress the influence of the so-called short-channel effect. As long as a gate electrode is composed of a semiconductor material, it is difficult to effectively suppress the depletion of the gate electrode, which is one of factors in the short-channel effect. To address this problem, there has been proposed a scheme in which a gate electrode is formed by using a conductive material such as a metal or metal compound. As a method for forming a gate electrode by using a conductive material, there has been proposed a method in which e.g. a metal film is deposited instead of a polycrystalline silicon film and this metal film is patterned to thereby form a gate electrode similarly to related-art methods. Furthermore, there has also been proposed a method in which a gate electrode is formed by a so-called damascene process of burying a conductive material in a gate electrode formation opening (refer to e.g., Atsushi Yagishita et al., “High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1 μm Regime,” International Electron Devices Meeting 1998 Technical Digest p.p. 785-788 (1998) and Japanese Patent Laid-Open No. 2005-303256). In the method of forming a gate electrode by a damascene process, a gate insulating film composed of e.g. an insulating material (e.g., hafnium oxide) having a relative dielectric constant higher than that of silicon oxide is formed in a gate electrode formation opening arising from removal of a dummy gate electrode, and then a gate electrode is formed. This method can enhance characteristics of the insulated gate field effect transistor.
The outline of a method for forming a gate electrode by a related-art damascene process will be described below with reference to FIGS. 1C, 1D, 1E, 1F, 5A, and 5B, which are schematic partial end views of a silicon semiconductor substrate and so on.
[Step-10]
Initially, a base 10 is prepared that includes source/drain regions 13, a channel forming region 12, a gate insulating film 30 that is formed on the channel forming region 12 and composed of hafnium oxide, an insulating layer 21 that is composed of SiO2 and covers the source/drain regions 13, and a gate electrode formation opening 22 that is provided in a partial portion of the insulating layer 21 above the channel forming region 12 (see FIGS. 1C and 1D).
A method for manufacturing the base 10 will be described in detail later in the explanation of a first embodiment of the present invention. In the drawings, reference numeral 11 denotes a silicon semiconductor substrate. Reference numeral 13A denotes a silicide layer formed in upper part of the source/drain regions 13. Reference numeral 17 denotes a side wall film.
[Step-20]
After the preparation of the base 10, a work function control layer 31 composed of a metal material (hafnium silicide) for defining the work function of the gate electrode and a barrier layer (not shown) composed of TiN are sequentially formed across the entire surface (see FIG. 1E). Thereafter, a conductive material layer 32 composed of tungsten is formed across the entire surface based on so-called blanket tungsten CVD. Subsequently, planarization treatment based on CMP is carried out to remove the conductive material layer 32, the barrier layer, the work function control layer 31, and the gate insulating film 30 over the insulating layer 21 and the side wall film 17. In this manner, a gate electrode 23 can be obtained (see FIG. 1F). The gate electrode 23 is formed above the channel forming region 12 with the intermediary of the gate insulating film 30 therebetween and is formed of the work function control layer 31, the barrier layer (not shown), and the conductive material layer 32.
[Step-30]
Subsequently, an interlayer insulating layer 142 composed of SiO2 is formed by e.g. high-density plasma CVD across the entire surface (see FIG. 5A).
[Step-40]
Subsequently, based on photolithography and dry etching, contact plug formation openings 43A and 43B are formed in partial portions of the interlayer insulating layer 142 above the gate electrode 23 and above the source/drain regions 13. Thereafter, a second barrier layer (not shown) composed of Ti (lower layer)/TiN (upper layer) is formed across the entire surface and then a tungsten layer is formed across the entire surface based on blanket tungsten CVD. Subsequently, planarization treatment based on CMP is carried out, so that contact plugs 44A and 44B can be formed in the contact plug formation openings 43A and 43B (see FIG. 5B).